1. Field of the Invention
The present invention relates generally to the field of integrated circuits formed on a semiconductor substrate, such as a silicon wafer or die, including vias formed therethrough and, more particularly although not necessarily limited to, semiconductor substrates that include through-vias filled with conductive material and methods for their fabrication.
2. State of the Art
In order to function, integrated circuits must be in electrical communication with signal inputs and outputs as well as power and ground or bias connections external to the integrated circuit. For example, power and ground or other reference voltage must be supplied for operation of the integrated circuit, and other connections, such as for input, output and timing signals, may also be required. These connections are typically made through leads or other conductive elements connected to bond pads present on the active surface of a semiconductor die.
As electronic devices have become smaller and more sophisticated, the challenge of expanding capabilities while minimizing the space, or “real estate,” used by an integrated circuit has continued to increase. Techniques for reducing the space required by a semiconductor die or chip include the use of a redistribution layer (RDL) as an additional level of wiring to reposition bond pads providing inputs and outputs for a semiconductor die from the perimeter or along the centerline to alternative locations, for example, to define an array of locations for flip-chip attachment to a substrate. Use of bond pad redistribution may be necessary if perimeter or central bond pads have to be rerouted into another I/O layout. For example, if perimeter or central bond pad pitch (spacing) is too fine or is otherwise unsuitable for connection to the terminal pad layout of a carrier substrate, repositioning may be required.
Where present, the traces of an RDL may be embedded into a dielectric material. Suitable dielectric materials may include benzocyclobutene (BCB), polyimide, and photosensitive dielectrics. The process steps depend on whether the redistribution traces are aluminum or copper. For aluminum traces, the aluminum is sputtered onto the wafer surface and the traces are etched using a photolithography-defined etch mask pattern comprising a resist. In the case of copper traces, the metal is electroplated onto the wafer surface and then selectively etched to form traces. A redistribution layer is typically applied on the active surface of a semiconductor die to enable flips chip mounting of the resulting “chip-scale” package on a carrier substrate such as an interposer or a printed circuit board.
Another technique for reducing the real estate required on a carrier substrate is the use of stacked semiconductor chips in a single package. In stacked chip-scale packages, two or more semiconductor chips will be mounted in a stack and electrically interconnected to a carrier substrate and/or to one another. This reduces the space taken on the underlying carrier substrate in comparison to mounting separate chips directly to the substrate.
Stacked chip-scale packages may require vias to be formed through the entire thickness of a semiconductor die between the active surface and backside thereof, allowing electrical connection therethrough to one or more dice stacked thereon. Such vias may require high aspect ratios (the ratio of via depth to diameter) due to the limited available area for positioning the vias in the semiconductor die, making them difficult to fill with electrically conductive material. Electroless plating of vias with a conductive material typically requires the placement of a seed layer of conductive material, such as copper or aluminum, in the via. Typically, this is accomplished by a sputtering or chemical vapor deposition (“CVD”) process, which can experience difficulty in depositing the conductive material on the bottom of a relatively high aspect via, for example, 0:1 or greater. Such high aspect ratios via may even have aspects of 15:1 or greater. Where a portion of the seed layer is deposited on the side of a high aspect ratio via, the material depositing during filling can fill across the via above the bottom, funneling or bridging off the underlying portion of the via. Other techniques, such as depositing conductive material over the surface of the wafer to fill the vias can similarly lead to the funneling or bridging off of a high aspect ratio via near the top of the via. Conventional electroplating typically requires the via to be open on both ends to enable a conductive contact plate to be placed on one side of the wafer to cover the bottom of the via and the electroplating solution to enter the via from the other side. This technique thus may limit the placement or order of the via fill in the wafer fabrication process. Some electroplating techniques also may require placement of a seed layer, resulting in similar funneling or bridging off problems. For example, a relatively new process employs metal organic chemical vapor deposition (MOCVD) to place a copper seed layer prior to electroplating of copper in the via. In addition to the extra step required to place the seed layer, there are reliability issues with this approach.
Accordingly, a method or system for effectively filling high aspect ratio vias without the need for placing a seed layer would be an improvement in the art. Such a technique that might be used for filling blind (or closed end) vias would constitute a further improvement in the art.